Optimization of in-plane SiC capacitive accelerometers design parameters

This paper introduces methods to find the design parameters that result in the best sensitivity for a given in-plane differential capacitive accelerometer. We show how to find the optimum electrode length for a device of a specific design area. Design and simulation results for a CMOS-compatible single-axis silicon carbide accelerometer are reported, based on the methods proposed here. The accelerometer uses two supporting beams to increase the device flexibility in the sensing direction, resulting in a 9.14 fF/g sensitivity. It has a total of 2.4% nonlinearity over a range of ±2 g, with a minimum detectable signal of 2.2 mg, when using a 20 aF resolution readout chip.