A Novel Wafer-Yield PDF Model and Verification with 90-150nm SOC Chips ISSM Paper: DM-O-038

In this paper, we describe a new wafer yield distri- bution model, which agrees well with experiment using fabri- cated products with various process technologies. To investi- gate physical reasoning of the proposed model, we firstly measure effective defect density of chips regarding to spatial dependency in a wafer. It is clarified that the defect density near wafer edge is a couple of times larger than that at the rest of wafer area. Note that the increase of defect at wafer edge causes a significant yield loss in production process lines.