High-Speed CMOS Color Stereo Camera with Low Complexity VLSI Implementation for Real-Time 3D Vision Applications

The paper presents alow complexity hardware architecture of CMOS color stereo camera for real-time 3D vision applications. To minimize the hardware complexity, two key ideas are applied. Firstly, a hardware architecture sharing line-by-line overlapped convolution kernels is proposed to reduce the number of arithmetic operations in demosaicing of bayer RGB images without image quality degradation. Secondly, an adaptive sync compensation module is proposed to synchronize master/slave image sensors, and display devices by compensating the sync signals period of slave image sensor and display devices in real-time, after monitoring varying periods of the master sync signals. In consequence, external memories such as SDRAM, that can be a considerable overhead in stereo camera implementation, is completely removed. The proposed hardware architecture is verified that the number of logic elements and registers of Intel Max10 FPGA (10M16DCU324I7G) is reduced by 69% and 76% respectively comparing to demo-saicing hardware without sharing and external memory based architecture. Also, the developed stereo camera can capture full-HD stereo images at 60 FPS and/or $\pmb{1920\times 1200\mathrm{p}}$ stereo images at 54 FPS. Moreover, it is more preferable in real-time 3D vision applications.