A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits

This paper describes a quad 3.125 Gbps transceiver focusing on digital data recovery circuits. Effect of each design parameters on jitter tolerance (JTOL) is analyzed and for better JTOL, a new phase-averaging method with internal forward path is proposed. On-chip JTOL measurement circuits are implemented to characterize the transceiver performance, and it shows that the proposed method improves the JTOL about 0.1 UI. Implemented in 0.13 CMOS, the transceiver tolerates up to 0.67 UI of total jitter at 3.125Gbps.