Micropower Incremental Analog-to-Digital Converters

Integrated sensor interfaces require energy-efficient high-resolution data converters. In many applications, the best choice is to use incremental analog-to-digital converters (IADCs) incorporating variants of extended counting. In this chapter, we discuss the design of a micropower IADC. By using a feed-forward architecture, the IADC accumulates the residue voltage, so various hybrid variants of extended counting can be implemented. Several such schemes are reviewed and discussed, as well as the trade-off between higher order modulators, higher oversampling ratio and energy efficiency. A two-step IADC is proposed, which extends the performance of an Nth-order IADC close to that of a (2N − 1)th-order IADC. A design example uses the circuitry of a second-order IADC to achieve a performance nearly equal to that of a third-order IADC. The implemented IADC achieves a measured dynamic range of 99.8 dB, and a SNDR of 91 dB for a maximum input 2.2 VPP and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS and operated from a 1.2 V power supply, the IADC’s core area is 0.2 mm2, and it consumes only 10.7 μW. The measured FoMs are 0.76 pJ/conv.step and 173.5 dB, both among the best reported results for IADCs.