Distal readout circuit self-triggering peak hold circuit

The present invention discloses a front end of the readout circuit from triggering a peak hold circuit for solving the problems of the prior art peak-hold circuit output voltage accuracy is low. Aspect is a potential holding capacitor Ch, the buffer, the delay circuit, a comparator and a switch. Input voltage Vi with a delay after the signal delay circuit delays the comparison, the intersection occurs between the input signal voltage Vi and the delayed, then the output of a comparator K flip the switch turned off, the peak hold the potential holding capacitor Ch. The circuit can generate a trigger signal internally when the input voltage Vi rises, the output voltage Vo is equal to the input voltage Vi. When the signal reaches a peak, the switch K is turned off. Due to the output voltage Vo no path to ground, may be maintained at the peak potential of the holding capacitor Ch, improves the accuracy of the output voltage. And the entire circuit is a digital circuit does not appear simple.