Multidimensional physical design optimization for systematic and parametric yield loss reduction

This presentation demonstrates one of Design-for-Manufacturing (DFM) solutions where a combination of design rules and lithography analysis (NILS, MEEF, and PW) is used as a basis for physical design correction and optimization. A physical design flow typically includes RET/OPC and post-OPC verification (Silicon DRC) steps. Error markers, generated at the verification step, show locations of so-called "hot spots" which are lithographically sensitive, areas prone to silicon failures. In our approach "hot spots" are traced back to a design and the design has been optimized to make those areas manufacturable. "Hot spot" markers of a flat post OPC layout are analyzed and categorized and only a unique instance of a "hot spot" is traced back to design hierarchy and corrected. Layout correction and optimization is guided by litho analysis and design intent. A set of lithography specific local constraints is added to a set of global constraints (DRC rules). A constraint-solving engine generates a new version of the layout that is DRC correct and is now "lithography/OPC friendly". Depending on a user accessible set of parameters, design correction could be done with or without polygons edge segmentation and without critical area increase. Different lithography technologies (such as immersion lithography with hyper NA) and different process models could be applied. Device electrical performance in conjunction with simulated and extracted silicon shapes is discussed. Layout correction is done on a minimum edge/polygon movement principle, which leads to DRC clean and LVS respectful solution.