Verifying RET mask layouts

Mask layouts with reticle enhancement techniques (RET) - including optical proximity correction (OPC), phase shift mask (PSM), Off-axis illumination, assist features (AF) - no longer closely resemble the design or wafer layouts. RET techniques are also applied with varying degrees of rigor to different portions of the layout, to constrain overall mask complexity while maintaining design requirements in critical areas. These factors make verifying RET mask layouts much more challenging. The simulation-based verification principle is straightforward: a wafer layout is simulated from the RET mask layout and compared to the intended design layout or 'target'. The required simulation technologies are mature and available today in commercial tools capable of handling large data files. The challenge in efficient verification is to establish comprehensive required for sub- wavelength lithography. Today, some simple criteria are inferred from the design or lithographic effects. Ideally, more specific information related to design 'intent' and tolerances should be built into the physical design for use in RET synthesis and verification, as well as in circuit and timing analysis. In this paper we explore emerging RET verification strategies that offer a high degree of flexibility and programmability. We will also illustrate how these techniques can take advantage of 'design intent' information embedded in the physical design, resulting in robust verification that is not confused by the complex tradeoffs required for today's sophisticated RET methodologies.