A hardware implementation of intelligent ECG classifier

Purpose – The purpose of this paper is to design an intelligent ECG classifier using programmable IC technologies to implement many functional blocks of signal acquisition and processing in one compact device. The main microprocessor also simulates the TSK neuro-fuzzy classifier in testing mode to recognize the ECG beats. The design brings various theoretical solutions into practical applications. Design/methodology/approach – The ECG signals are acquired and pre-processed using the Field-Programmable Analog Array (FPAA) IC due to the ability of precise configuration of analog parameters. The R peak of the QRS complexes and a window of 300 ms of ECG signals around the R peak are detected. In this paper we have proposed a method to extract the signal features using the Hermite decomposition algorithm, which requires only a multiplication of two matrices. Based on the features vectors, the ECG beats are classified using a TSK neuro-fuzzy network, whose parameters are trained earlier on PC and downloaded int...