Requirements and results of a full-field EUV OPC flow

Now that full-field alpha EUV scanners are available to lithographers at multiple sites around the world, there is greatly increased demand for full-field EUV circuit and teststructure wafer images. Successful patterning of these circuit and teststructure wafer images requires mask layout data which accurately compensates for all expected process transformations occurring in the EUV patterning process. These process transformations include flare, optical diffraction, resist behavior, mask shadowing, and 3D mask electromagnetic effects. In this paper, we present a complete fullfield EUV mask data correction flow which incorporates compensation for patterning transformations due to very long range flare, reflective multi-layer masks, thick mask absorbers, off-axis EUV scanner illumination, field-dependent shadowing and orientation dependent shadowing. Optimized algorithms for flare and mask effects now enable both fast and accurate full-chip process effect compensation. Results are shown for both the 22nm and 16nm logic device nodes. The results are presented by error component category to highlight the relative importance of each effect.