A low voltage, low noise CMOS RF receiver front-end

This paper presents a low-power, low-voltage radio frequency (RF) receiver front-end implemented in a 0.18 /spl mu/m CMOS process that is intended for 2.4 GHz wireless applications. It includes a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a passive switching direct downconversion mixer. The LNA has a simulated noise figure of 0.75 dB and power gain of 12.9 dB. With a -30 dBm RF input and a 0.45V LO signal, the mixer has a simulated noise figure of 7.8 dB, conversion gain of -2.2 dB, 1-dB compression point of -8 dBm, input third-order intercept point (IIP3) of 14.4 dBm. Comparison between this work and others have shown better noise performance and less power dissipation.