IDeF-X HDBD:low-noise ASIC for Spectro-imaging with semiconductor detectors

IDeF-X HDBD is the new version of a family of integrated circuits dedicated to the readout of semiconductor detectors. It is a 32-channel Application Specific Integrated Circuit designed to read charges ranging from -40 to 40 fC. The circuit was optimized for small detector capacitances (<1pF) and low leakage current (<1nA). The chip allows to reach an Equivalent Noise Charge floor (ENC) of 17 el.rms. It has a self-triggering capability allowing multiple types of readout either only hit channels, selected channels or all channels. Each channel is based on a scaled charge sensitive amplifier follower by a CR-RC² filter and a peak detector with a pile-up rejection system allowing memorizing only the first arriving charge. Each channel has a power consumption of 850 µW. Gain and shaping time are tunable. This circuit has been designed with radiation mitigation techniques allowing it to handle a dose up to 300 krad and a Single Event Latchup (SEL) threshold of 65 MeV.cm²/mg suitable for space applications. This ASIC can read either Cadmium Telluride or Silicon detectors for instance for imaging-spectroscopy applications.