An Adaptive Overlap-Pipelined Multitasking Superscalar Processor

Low power consumption, high performance, and small die size are the three essential considerations in modern CPU design, from tiny IoT devices to General Purpose Manycore System-on-Chip. With these considerations, we introduce a new CPU design that features Adaptive Overlapping Multitasking pipelines, to better balance the design tradeoffs of the traditional scalar and superscalar CPUs. By providing dynamic reconfigurability, we enable user applications to decide at run-time whether to run the CPU in a high-performance or a low-power mode, to meet their respective application deadlines or power budgets. The low-power mode also provides redundancies that allow the CPU to continue operating, even when some of its pipeline stages are damaged. We used the RISC-V ISA test suite, Dhrystone, Coremark, and ten other benchmarks to validate our CPU design's functionality and performance. Our CPU can consistently deliver up to 2.0 Instruction Per Cycle and score a 3.924 DMIPS/MHz and 6.556 Coremark/MHz with Dhrystone and Coremark benchmarks.