Analysis and Measurement of Power Integrity and Jitter Impacts on Thin-Core and Coreless Packages

Advanced memory technologies such as DDR4 and LPDDR4 are able to receive and transmit huge amount of data in faster and more efficient ways than ever before. At the same time, reducing power noise and designing dense traces become a challenging part of the design processes. In particular, high signal density on a package naturally restricts the resources for robust power delivery when keeping the same package layer count. While the costly thin-core packaging technology is widely available, embedded trace substrate (ETS) packaging technology is another viable solution at a reduced price. This work employs ETS substrate with careful signal designs and deployments of power planes. Essential part of the ETS package design includes the power delivery network (PDN) design in conjunction with Power Supply Induced Jitter (PSIJ) sensitivity from the silicon circuits. At the same time, critical components of the power rail noise needs to be suppressed by on-die and on-package decoupling capacitances. After iterative designs and simulations for ETS package, about 92% of overall PDN noise and 86%~95% of jitter impact were estimated compared to thin-core package, and 88% of tJIT(per) and 93% of tJIT(cc) have been achieved in the measurements.