FDTD/spl I.bar/SPICE analysis of EMI and SSO of LSI ICs using a full chip macro model

A method of macro modeling the power and ground circuits of an LSI IC taking into account internal gates has been proposed. Major contributors to simultaneous switching output noise (SSO) and electromagnetic interference (EMI) are the power and ground currents of clock circuits in internal gates which are modeled using simple flip-flop circuits by summing their gate widths and interconnection capacitances. Using such a macro model, methods for reducing SSO and EMI for such LSI chips are analyzed by FDTD/spl I.bar/SPICE. It is shown that the major contributor to SSO and EMI is not I/O circuitry but internal gates. The most effective way to reduce such noise is to implement large decoupling capacitors into a chip.