Unsafe Writing Impacts on the Stateful Memristor Gates

Memristor-based stateful logic demonstrates a method of in-memory computing, which is a promising way to overcome the data-transfer bottleneck in the current von Neumann computer architecture. However, due to the instability, the memristor device exhibits an inherent stochastic switching behavior especially when the applied voltage is in the switching range of unsafe writing. In such case, the delicate design of stateful memristor gates could suffer the reliability problem. Here, such unsafe writing impacts on the memristor-based logic operation is systematically analyzed. Through establishing the Markov chain model of unsafe writing effects, we deduce the mathematical relationship between the material implication (IMP) logic gate reliability and switching probability. It reveals that unsafe writing with enough operation time would make the IMP logic converge to always True logic. The best operation time for the unsafe write is then proposed to improve the probability of right logic function and avoid the undesired logic result, which is demonstrated with simulation.