Active Silicon Interposer for Heterogeneous Integration: System Scaling and Cost Effectiveness

Achieved system scaling by implementing key system functions into active interposer. Demonstrated partitioning of System on Chip (SoC) to smaller dies to achieve lower cost and higher yield. Heterogeneous integration involving 130 nm active silicon interposer, 65 nm split I/O chip and 28 nm FPGA die is demonstrated. A cost model was developed for this integration approach and it confirmed that the system scaling and cost reduction is higher for advanced nodes.