Decoder with the dynamic CMOS matrix

This paper presents the Full Custom Design technique in the IC digital design, which is used to achieve the maximum performance or minimum power. The technique was applied on the decoder of the ARM1 register file. Presented research combines a static CMOS logic and a dynamic logic, which has higher speed than the equivalent static family. The validation of the design is made by the SPICE3 simulator (BSIM3 model) considering RC parasitic values of metal wiring. Our results demonstrate the size of the register file decoder and behavior of the dynamic matrix.