Numerical analysis of tunneling current due to electric field concentration at gate edge of polysilicon/SiO2/silicon structures

Tunneling current enhancement due to electric field concentration at a gate edge is investigated by numerical calculation. The detailed current distribution and change of current-voltage ( I-V) characteristics are calculated for several gate geometries differing in curvature radius. It is shown that the current density of an MOS structure with an oxide thickness of 12 nm varies by 3 orders of magnitude when the curvature radius at the gate edge changes from 30 nm to 2 nm. A very narrow region of 8 nm at the curvature area is responsible for 80% of the total current between the gate and n+ region. The calculated change in I-V characteristics is consistent with the experimentally measured I-V curve of a polysilicon gate/SiO2/n+-silicon structure.