Investigation of Scaling and Temperature Effects in Total Ionizing Dose (TID) Experiments in 65 nm CMOS

Ten-fold radiation levels are expected in the upgrade of the High-Luminosity Large Hadron Collider (HL-LHC) at CERN. Bulk silicon CMOS at 65 nm offers appreciable advantages among cost, performance, and resilience to high Total Ionizing Dose (TID). In the present paper, geometrical scaling of key analog design parameters of MOS transistors irradiated at high TID is investigated. Experiments are carried out for TID of 100, 200 and up to 500 Mrad(SiO 2 ) and at −30°C, 0°C, and 25°C. We find that parameters are least degraded at −30°C. However, short-channel NMOSTs show a significant degradation of slope factor, which is more severe at 0°C than at 25°C. In contrast, the slope factor in short-channel PMOSTs shows lowest sensitivity to high TID.