БЛОК КОЛЬЦЕВЫХ ГЕНЕРАТОРОВ ДЛЯ ВЕРИФИКАЦИИ НА КРИСТАЛЛЕ ЗАДЕРЖЕК СТАНДАРТНЫХ ЦИФРОВЫХ ЭЛЕМЕНТОВ

Functionality and electrical parameters of complete products, such as standard cell libraries, must be silicon-proven. One of the most important parameter of standard cells is propagation delay. Discrepancy between real values of this parameter and its declared values may result in yield loss. In this paper we describe efficient on-chip standard cell delay verification technique. We present this technique implementation and discuss its possible sources of measurement error. The recommendations on designing and testing analogous blocks are given. Also, the scheme of flip-flop delay verification is proposed. Designed block allows verifying delays of 20 different standard cells. In total, 72 delay measurement cells are placed in the block for estimating local on-chip variations. The CAD simulation of the designed structure shows maximum delay error related to measuring circuit to be 3 ps. Dimensions of the block are 105x145 pm 2  in 90 nm technology node. Four such blocks are integrated on test chip to estimate spatially-correlated delay variations.