A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategy

Advances in silicon technology bring high-performance mobile devices and networks that connect people all over the world. In the meantime, data centers with high computational capabilities boost the prosperity of the social world. Emerging data centers keep requiring higher density memory, with higher data rates for processing large amounts of data. However, the implementation of high density DRAM is hindered by large chip area, causing degradation of the power distribution network (PDN) and higher yield losses due to the higher probability of die defects. This paper presents a 16Gb 3.2Gb/s/pin DDR4 SDRAM that features an improved PDN and a repair strategy. The PDN is reinforced by power pads with regulators in the middle of the bank area and a staggered power-up scheme for 3D stacked (3DS) DRAM. Yield is enhanced by introducing ECC for redundant cell operation and by developing an advanced built-in self-repair scheme that automatically corrects bit-errors at the application level.