Design and analysis of DMA based network interface for NoC's router

Recently Multi-core Globally Asynchronous Locally Synchronous(GALS) architecture emerged as the de facto to solution to satisfy the performance requirement of mainly modern embedded applications. Due to scalability, flexibility, and high bandwidth properties, Network-on-chip (NoC) technique has been proposed as a promising solution for the communication-centric platform. The rapid introduction of NoC for the multi-core GALS architecture requires proper Network-Interface (NI) design to interface two different IP blocks via network routers within the same chip. This paper proposed a DMA based Network-Interface for con-necting the NoC router to a processor element. This proposed NI has three memory mapped registers, Read packet register, Write packet register, and Status packet register. Considering the current trend towards multi-core GALS architectures and the critical role, the interconnect plays in the whole system, this paper focuses on proposed NI design with its performance analysis in term of power, area, and delay using RTL NI model. The RTL coding is performed using Verilog HDL and simulation with implementation is performed by the Xilinx 14.7 and FPGA Vertex 6 as the target technology.