MOSFET RF performance improvement through spacer profile optimization for 28nm Poly/SiON SoC technology

As the MOSFET scales down, with keeping increasing of speed (ft), minimum noise figure (NF) is difficult to scale down where increasing gate resistance (Rg) is one of crucial impact factors. In this paper, we present a novel approach to boost MOSFET RF performance by spacer profile optimization. It can help reduce Rg about 12% and increase Fmax about 7% for critical size device (L=27nm) without degrading device DC performance on 28nm Poly/SiON technology platform. This approach does NOT introduce any extra steps into process flow and can be easily combined with those traditional Rg reduction methods.