Design and analysis of logarithmic digital quantizers with applications to low-power data interfaces for speech processing

Traditionally, digital voice-band systems have employed either uniform, $\mu$-law, or A-law encoding. The compressive characteristics of $\mu$-law or A-law encoding result in an economical data representation while not impairing perception. However, if signal processing functions, most of which involve linear operations, are to be performed directly on the digital signals then it has been necessary, before processing, to convert the log-PCM data into a linear format. Motivated by the need for low-power analog interfaces to provide data to several special-purpose logarithmic digital signal processors currently under development, this dissertation explores the properties of sign/logarithm encoding. This allows special-purpose processors to perform operations directly on the logarithmically encoded data. Moreover, it is shown that this approach results in performance quite similar to that exhibited by traditional compandors. Quantization noise characteristics for the case of a finite word length are derived. Also, the effects upon system performance when input signals possess a non-zero mean are presented. Performance degradation due to harmonic distortion, introduced by mismatches in the logarithm base among different subsystems, are quantified. Simple, power-efficient converters are then proposed based upon the switched-capacitor equivalent of a parallel RC network and factoring of the digital data. The effects of nonidealities in the active and passive components on coder performance are also established. In order to demonstrate the usefulness of the proposed encoder-decoder, the design of an experimental Analog Interface Processor (AIP) for use in a Digital Hearing Aid (DHA) is described. This experimental prototype includes, in addition to the data conversion circuits, an anti-aliasing filter, a low-noise preamplifier, and several spectral shaping circuits. Finally, experimental data obtained from circuits fabricated in a standard 2 $\mu$m, bulk CMOS, double-poly process are presented. The AIP, when completed, is estimated to consume approximately 500 microwatts and occupy an area of only 16 mm$\sp2.$