Poly Gate Proximity Effect Modeling for 40nm CMOS

A new compact and scalable psp model for the layout proximity effect of poly gate in 40nm CMOSFET is proposed. This model takes into account the impact of gate space and neighboring gates number on mobility and flatband voltage. With the silicon verification, saturation current change up to 5%–7% and flatband voltage change up to 6-8mv is modeled in the constructed model. Vthlin, Idlin and Gmmax are also monitored. These good results show the importance of the new model for circuit design in advanced CMOS node.