Gate Ratio Balancing을 이용한 Multi-Corner CTS 최적화 기법

Recent SoC (System on Chip)must take into account more process corner due to node scaling than before. That imposes severe strain on TAT (Turn Around Time) and timing closure. One of the most important timing related stage is CTS (Clock Tree Synthesis) in physical design loop. Existing CAD (Computer Aided Design) SW carries out CTS in consideration of only one process corner in general. However, above all things, it is important that it reduces timing variation under multi-corner condition in performing CTS. We observe that the timing between cell and wire are quite different and this occupies considerable portion of variation gap. In this paper, we propose the multi-corner CTS exploiting "Gate Ratio Balancing". According to the result, skew is reduced by 25% on average when proposed method is applied to the designs using 45nm node technology. In addition, hold timing total negative slack(TNS) is reduced 20%. Consideration of multi-corner will become inevitable, as process node shrinks and design complexity is gradually increasing. Therefore, "Gate Ratio Balancing"can be a promising solution to improve the CTS performance under multi-corner condition.