Optimizing DDR5 address signal integrity using stochastic learning algorithms

With DDR5, the DRAMs will have the ability to support On Die Termination (ODT). The address topology is expected to continue to be a fly-by topology, with each DRAM loading the address bus driven by the controller. Each DRAM is expected to allow multiple ODT settings. The number of potential settings grows exponentially with the number of DRAMs in the system. Finding the optimal setting within the valid option space becomes a challenge with large number of DRAMs. At the same time, finding this optimal setting also becomes critical at the data rates of DDR5.