Self-Dynamic and Static Biasing for Output Power and Efficiency Enhancement of Complementary Antiparallel Diode Pair Frequency Tripler

A 157-GHz complementary antiparallel diode pair (CAPDP) frequency tripler using a combination of self-dynamic and static dc biasing to enhance output power and conversion efficiency is demonstrated in 130-nm complementary metal-oxide-semiconductor. The self-dynamic biasing expands the off-zone of CAPDP to reduce the output power roll-off at high input levels. A negative static dc bias tunes the off-zone to enhance the nonlinearity to increase the output power at low input levels. The frequency tripler generates -18.6 dBm maximum output power (POUT) at 157.5 GHz at the input power (PIN) of 13.4 dBm. At PIN of 11 dBm, POUT is 2.7-dB higher or conversion loss (CL) is 2.7-dB lower than the tripler with a cathode-tied CAPDP. At PIN greater than 13.4 dBm, POUT should be more than 4.3-dB higher and CL is more than 4.3-dB lower.