A proposal of LDMOS using Deep Trench poly field plate

In this paper, we developed Deep Trench structure of LDMOS instead of STI in conventional one, with 0.18um 60V BCD process. By forming vertical drift region using Deep Trench, we achieved lower Ron.sp from cell pitch shrink while BVdss does not change. As a result we achieved 76V BVdss and 49.3 mohm∗mm2 Ron.sp of low side 60V rated LDNMOS.