Design of a Low Power 2.4 GHz LNA

A 2.4 GHz CMOS low noise,low consumed power amplifier was designed,and the theories of the noise matching was presented.This amplifier was comprised of the classical cascade structure and the capacitor Cex added between the gate and the input source of MOSFET in order to meet the conjugated matching and noise matching simultaneously.The circuit is implemented with the SMIC 65nm CMOS technology and simulated by Cadence.The results show that the consumed power is less than 7 mW under the 1.2 V supply,noise figure is less than 0.7 dB and the gain is larger than 21 dB.It is unconditionally stable.The whole layout occupies 0.57 mm×0.65 mm.