CPW and discontinuities modeling for circuit design up to 110 GHz in SOI CMOS technology

This paper presents a new modeling method for integrated coplanar wave guides (CPW) and CPW discontinuities implemented in silicon on insulator (SOI) CMOS technology. Empirical equations, which are fitted to 3D EM simulations, are used to describe the electrical behavior of CPW as a function of the line's geometrical parameters. The models are validated through measurements up to 110 GHz. Thanks to accurate full wave simulations, discontinuities such as underpasses, 90deg bends, and tee and cross junctions are improved, and electrical models are developed. All models are easily implemented in commercial CAD tools. Finally, a 60 GHz band-pass filter is designed applying the described models and the simulations are compared to measurements.