A 9.6 mW Low-Noise Millimeter-Wave Sub-Sampling PLL with a Divider-less Sub-Sampling Lock Detector in 65 nm CMOS

A 40.5 GHz sub-sampling phase-locked loop (SSPLL) with only 9.6 mW power consumption is presented. The proposed Sub-Sampling Lock Detector (SSLD) samples the output signal with on-chip generated 900 MHz reference, and can automatically detect and rectify the unlock or locked-to-wrong-harmonic states. This is done without using traditional power-consuming divider-based frequency-locked loop (FLL). The proposed SSPLL hence achieves low power, low in-band phase noise and robust operation simultaneously.