256/spl times/256-pixel CMOS digital camera for computer vision with 32 algorithmic ADCs on board

The authors present a CMOS digital camera for computer vision which integrates on a chip a 256/spl times/256-pixel photosensitive array together with 32 charge amplifiers and ADCs (one every 8 pixel columns), timing and control circuitry and a digital interface with an external microprocessor. An innovative implementation of algorithmic analogue-to-digital conversion was used in the design of the core cell for a compact converter array. The circuit offers a good trade-off between architectures based on sensors with a single video-rate converter and those based on sensors with a large number of lower-rate converters (one per pixel column). Fabricated in a standard 1.2-/spl mu/m CMOS process with an added metal-3 light-shielding layer, the circuit requires a single supply voltage and occupies a total area of 50 mm/sup 2/. A thorough electro-optical test of the camera showed good performance in terms of sensitivity and spectral responsivity. Image quality adequate for computer vision was demonstrated.