Enabling faster design and implementation decisions using virtual prototyping

Wafer level packaging, embedded chip packaging, 2.5D/3D integration have picked up considerable topics as smaller package. Fan-out wafer level package (FO-WLP) is an especially ubiquitous package in use today. FO-WLP reduces cost, increases I/O density and integration, reduces package size and thickness, and improves electrical and thermal performance. It enables the creation of ball and fan-out from a die independent of die size and supports the placement of multiple die. It provides much design flexibility. An effective and efficient implementation of FO-WLP designs require a careful planning of the interconnectivity between all parts of the package. In order to optimize the chip, package, and board interconnect, to reduce costs (design and manufacturing), and to minimize risk, early prototyping is highly recommended. In this study, we used a single tool platform to perform rapid virtual prototyping of a complex FO-WLP package-on-package design to consider routability, package cost, and manufacturing issues. Using chip design prototyping features, we were able to quickly iterate between multiple implementations of the die and package to find the optimal solution. We confirmed that the wafer-level package data was exported and accepted by the reticle maker.