New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism
2010
Recent advances in the semiconductor industry enable the integration of many processing units on a single die and new processors are often included into large many-core SoCs. The dependability of such a many-core processor is essential for many mission-critical applications. Ideas such as the Know-Good-Tile concept [1] or majority-voting among tiles [2] have been proposed to explore the possibility to enhance the dependability of a many-core processor.
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