Electrical coupling in multi-array charge coupled devices

Silicon based charge coupled device (CCD) performances have improved immensely over the years. Scientific community across the globe target challenging remote sensing applications with CCD as optical imaging detector. Over the years, both pixel count (from few hundreds to few tens of thousands) and line readout rate (from few kHz to few tens of kHz) have increased considerably. Pixels are readout using a large number of output ports driven up to few tens of MHz Moreover, for multi-spectral applications, same Si die contains multiple arrays sharing input stimuli. This is usually done to optimize package pin count. Si die as well as package level layout of clock and bias lines become critical for closely spaced multi-array devices. The inter-array separation may go down to few hundreds of microns when filter coating is laid on top of the die. Die level layout becomes quite critical for devices with such architecture. The inter-array (consecutive arrays) separation is optimized to reduce optical coupling / stray light in devices integrated multi-band strip filter. Layout constraints along with shared bias/clock lines are known to produce electrical cross-talk or coupling. Effect of this (within one array or between two arrays) cross-talk is more pronounced in systems having low noise floor. Video signal dependent coupling in a multi-port system becomes quite complex and leads to a relatively noisier system (post correction). The paper presents results of simulations and tests (pre and post correction) addressing this type of electrical coupling. The paper presents cause, impact and possible remedial measures to minimize such coupling in a multi-array, multi-port TDI CCD from 1.3% to below 0.06%.