Tunnel oxide and ETOX/sup TM/ flash scaling limitation

The intrinsic tunnel oxide thickness limit is around 6 nm due to direct tunneling. In practical devices, the limit is 8 nm due to stress induced leakage after program and erase cycles. Nitridation reduces electron trapping but does not decrease the lower thickness limit. Operating voltages also do not scale well in flash memories. Voltages required for operation range from 10-12 V for channel hot electron stacked gate devices to up to 20 V for Fowler-Nordheim tunnel/erase devices. This places limits on transistor channel and isolation scaling. Looking ahead, cell scaling beyond 0.13 /spl mu/m will be difficult unless there is a major breakthrough. Multilevel cell storage technology provides a cost effective alternative to process scaling. Feasibility studies showed that up to 16 levels or 4 bits per cell is possible with stacked gate technology. Stacked gate flash memory cells using channel hot electron programming are best suited for high density multilevel cell technology.