Package clock distribution design optimization for high-speed and low-power VLSIs

With continually increased difficulties of the clock distribution in high speed microprocessors and application-specific integrated circuits (ASICs), the package clock distribution shows very promising advantages. The concurrent design of chip and package will provide the optimal design of a clock network by taking the advantages of package layers. The package layers provide 1000 times less wire resistance and 10 times less wire capacitance than those of interconnects on chip. Therefore, it is more beneficial to route the global clock network on package. The implementation issues of the package clock distribution are described in this paper, including the electrostatic discharge (ESD) circuit design for local clock buffers and transmission line noise suppression for package clock trees.