Impact of Passive & Active Load Gate Impedance on Breakdown Hardness in 28nm FDSOI Technology.

The impact of integrated gate impedances, passive (polycomb, R G ) and active (Input/Output MOSfet, Z load ), on the breakdown (BD) behaviors of 28nm Fully-Depleted Silicon-On-Insulator (FDSOI) transistors is discussed. It has been shown that R G and Z load affect directly the BD hardness of the devices. By reducing the BD hardness, a catastrophic failure of gate dielectric meaning complete loss of device functionalities can be avoided. Many configurations of R G , Z load are considered to obtain the best compromise in terms the BD hardness and functionalities of Device Under Test (DUT).