A study of cycling induced degradation mechanisms in Si nanocrystal memory devices.

The endurance of Si nanocrystal memory devices under Fowler–Nordheim program and erase (P/E) cycling is investigated. Both threshold voltage (Vth) and subthreshold swing (SS) degradation are observed when using a high program or erase voltage. The change of SS is found to be proportional to the shift of Vth, indicating that the generation of interface traps plays a dominant role. The charge pumping and the mid-gap voltage methods have been used to analyze endurance degradation both qualitatively and quantitatively. It is concluded that high erase voltage causes severe threshold voltage degradation by generating more interface traps and trapped oxide charges.