SOC Power Management Strategy Based on Global Hardware Functional State Analysis

Dynamic power management (DPM) has become a major technique for reducing power consumption in SoCs. One of the main challenges in DPM is to predict as soon as a component enters in idle mode if it will stay in this mode for a time longer than a minimum value that leads to power savings. Even if a component in power off state does not consume any power, waking up such a component induces a time penalty before it returns in running mode which impacts application performances. Moreover, the activity of components in any architecture depends on the mapping and scheduling of application tasks onto these components. These dependencies cannot be captured if power management decisions are taken on a per-component basis. Therefore, we propose a DPM technique based on a history of global states of the system where a global state is a collection of individual states of components at a given time. As a consequence, observing global state transitions at component level provides relevant information which help in taking decision to power off components and to anticipate their wake-up instants.