Synonym hit RAM; a 500 MHz 1.5 ns CMOS SRAM macro with 576 b parallel comparison and parity check functions

Recently, the capacity of first-level caches has increased to 32-64kB, improving microprocessor performance. In a large-capacity cache that operates at high speed, address translation delay is not negligible and a virtual cache without address translation is essential. As cache size increases, synonyms will be a serious problem because of ambiguity in address translation. The synonym hit RAM overcomes this problem. This RAM features a 500MHz CMOS SRAM macro with 576b parallel comparison and parity check functions. Use of a source-coupled logic (SCL) circuit for the comparator is essential to obtaining 1.5ns access time for comparison.