A method for selectively removing a spacer in a dual stress liner procedure

A method comprising: Forming a dielectric layer stack on a first transistor and a second transistor, each having a sidewall spacer structure, wherein the dielectric layer stack having at least an etch stop layer, a first strain-inducing layer thereon and a Atzsteuerschicht which is formed over the first stress-inducing layer; Performing an etch sequence for selectively removing a portion of the dielectric layer stack from above the second transistor, wherein the etch stop layer for controlling at least an etching process is applied in the etch sequence; at least reducing a size of the sidewall spacer structure formed on sidewalls of a gate electrode structure of the second transistor, while the sidewall spacer structure formed on sidewalls of a gate electrode structure of the first transistor is maintained; Forming a second stress-inducing layer above the first and the second transistor; and Removing a portion of the second stress-inducing layer from above the first transistor using the Atzsteuerschicht as an etch stop,