SYSCHECK: A user-programmable mixed-mode verification tool

A user-programmable verification tool for debugging mixed-mode IC and PCB (printed circuit board) systems has been developed. Using this tool, the designer can define checking rules regarding block properties, pin properties, and interconnections. Rule definition is performed through a 'zero-coding' interface. Advantages include reduced simulation time and enhanced design security. This tool has been fully integrated into a schematic capture tool, showing the feasibility of a direct coupling between such a system debugger and the design environment. A block design for a phase locked loop is considered as an example.