Thermal budget optimization on Strained Silicon-On-Insulator (SSOI) CMOS

In this paper, we have systematically investigated the impact of the thermal-induced stress relaxation on biaxially strained silicon-on-insulator (SSOI) CMOS. We found that STI anneal would degrade nMOS drive current by 12% but improve pMOS by 17% in long channel SSOI devices. However, skipping LDD anneal would increase extension resistance and cause performance degradation. In addition, it is found that narrow-width devices suffer more serious thermal strain relaxation. After optimizing the thermal process, we successfully demonstrate enhanced sSOI nMOS with 65% transconductance gain at L = 1 um and 15% drive current improvement at L = 40 nm over SOI nMOS.