Architectural enhancements in Stratix V

This paper describes architectural enhancements in the Altera Stratix-V" FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM block, and error correction that can correct up to 8 adjacent errors. Arithmetic performance is significantly improved using a fast adder with two levels of multi-bit skip. We also describe how the routing architecture and layout is optimized for the 28nm process to take advantage of a wider range of wire thicknesses offered on the different layers, and improvements in performance and routability are obtained without dramatic changes to the repeated floorplan of the logic plus routing fabric.