Current Research Trends and State-of-the-Art NoC Designs
2016
The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern massive multicore chips. However, with growing levels of integration, traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multihop metal-/dielectric-based interconnects. Three-dimensional integration, on-chip photonics, RF, and wireless links have been proposed as radical low-power and low-latency alternatives to the conventional planar wire-based designs. Wireless NoCs with carbon nanotube (CNT) or millimeter (mm)-wave metal antennas are shown to outperform traditional wire-based NoCs significantly in achievable data rate and energy dissipation. However, such emerging and transformative technologies can be prone to high levels of failures due to various issues related to manufacturing challenges and integration. On the other hand, several naturally occurring complex networks such as colonies of microbes and the World Wide Web are known to be inherently robust against high rates of failures and harsh environments. Adoption of such complex network-based architectures to design wireless NoCs enables wireless NoC architectures that have better achievable bandwidth, energy dissipation, thermal profiles, and fault tolerance over traditional wireline mesh architectures. This chapter focuses on current research in irregular NoC topologies, topology-agnostic routing, 3D, optical, and wireless NoC integration, and power- and temperature-aware design considerations.
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