A 1V 18 dBm 60GHz power amplifier with 24dB gain in 65nm LP CMOS

A 60 GHz 4-way power-combining power amplifier (PA) is realized in a 65nm LP CMOS. The PA consists of three common-source (CS) pseudo-differential stages, in which a capacitive neutralization is used to increase the reverse isolation and the maximum gain (Gmax). To achieve high gain within a small area, a new inter-stage impedance matching network is proposed, consisting of transformer, transmission line and shunt inductor. The PA exhibits a small-signal gain of about 24dB, with 3dB bandwidth of more than 10GHz. The saturated output power (P sat ) is 18 dBm and 19 dBm with 1 V and 1.2 V supply voltage, respectively. The peak PA E is 13.2% and P 1dB is 14.8 dBm. The PA occupies an area of 0.74mm 2 , including pads.