Automated Design and Optimization Of A CMOS OTA Using Geometric Programming

In this paper, a new design approach for low-power analog circuits is presented which uses an optimization algorithm to find the optimized values for transistor dimensions. Geometric Programming (GP) is used to find the globally optimal results using an optimization core. In this method, low power consumption is considered as the main objective along with considering other subjects such as gain and bandwidth. Using a feedback from HSPICE simulations, the best values for design variables can be achieved by continuously comparing the simulated results with the desired values and the acceptable error value. Finally, a folded-cascode structure is designed in 130nm CMOS technology to justify the performance of the proposed algorithm.